FIG. 1A (Prior Art) is a top-down diagram of a square portion of one type of conventional trench-type Insulated Gate Field Effect (IGBT) die. The square portion illustrated in FIG. 1A is replicated in rows and columns across the upper face of the trench IGBT die. FIG. 1B (Prior Art) is a cross-sectional diagram of the die taken along sectional line A-A′ in FIG. 1A. The plane illustrated in top-down perspective in FIG. 1A is the plane taken along sectional line B-B′ at the upper semiconductor surface in FIG. 1B. FIG. 1C (Prior Art) is a cross-sectional diagram taken along sectional line A-A″ in FIG. 1A.
As shown in FIG. 1A, multiple octagonal trenches are formed down into the upper semiconductor surface of the die. These octagonal trenches are disposed in a matrix of rows and columns. A gate oxide layer lines the sidewalls of each trench. A gate electrode of polysilicon in turn is disposed on the oxide layer in the trench. Reference numeral 1 in FIG. 1A identifies a gate electrode.
Reference numeral 2 identifies a grid-shaped N+ type emitter region that extends across the upper surface of the die. The grid-shaped N+ type emitter region 2 has the form of a set of interconnected strips of N+ type semiconductor material as illustrated. A grid-shaped P type body region also extends across the upper surface of the die. The P type body region includes a shallower and more lightly P type doped portion 3A as well as multiple deeper and more heavily P+ type doped portions. As seen in the top-down diagram of FIG. 1A, the shallower more lightly doped portion 3A of the P body region has a grid-shape and can be visualized as involving a plurality of parallel-extending vertical strips and a plurality of intersecting parallel-extending horizontal strips. One of the deeper P+ doped portions, also referred to as a sinker, is disposed at each intersection where a vertical strip of the more lightly doped portion crosses a horizontal strip of the more lightly doped portion. These deeper more heavily doped P+ type regions therefore are arranged in a two-dimensional matrix of rows and columns. Reference numerals 3B1, 3B2 3B3 and 3B4 identify four of these more heavily doped regions. As shown in the cross-sectional diagrams of FIGS. 1B and 1C, N+ type semiconductor material of the emitter region 2 forms a part of the outer sidewall of each trench.
If an appropriate voltage is placed on the trench gate electrode 1, then a conductive channel is formed in the shallower portion 3A of the P type body region immediately adjacent the trench. This channel extends vertically between the N+ type emitter region 2 and the N-type drift region 4 in FIG. 1C. If a voltage is placed on the metal emitter terminal 5 with respect to the metal collector terminal 6, then electrons will flow from the N− type emitter region 2, down through the conductive channel, and to the N− drift layer 4. This flow of electrons contributes to the overall current flow between metal emitter terminal 5 and the metal collector terminal 6. As is known in the art, holes are also injected from the P++ collector layer 7 into the N+ buffer layer 8. This flow of holes serves to increase the concentration of holes in the N− drift layer which in turn through conductivity modulation serves to increase the concentration of electrons in the N− drift layer. A higher concentration of electrons in the N− drift layer means that more electron current can flow through the device. In addition, holes that escape from the N− drift layer also contribute to the overall current flow between metal emitter terminal 5 and the metal collector terminal 6. Due to some of the current carrying capacity of the IGBT die being due to electron current flow in one direction, and due to other of the current carrying capacity of the IGBT die being due to hole current flow in the other direction, the device is said to be “bipolar”. The “B” in IGBT stands for bipolar.
In addition to these regions of the conventional trench IGBT of FIG. 1A, the convention IGBT die also includes numerous octagonal-shaped floating P well regions. There is one such octagonal-shaped floating P well region surrounded by each of the octagonal trenches. Reference numeral 9 identifies one such floating P well region.
If the trench IGBT is in the off state, and if a large reverse voltage is placed across the IGBT between the collector and emitter terminals, then there will be depletion regions formed on either side of the PN junction between the P body region and the N− drift layer. If the reverse voltage is great enough, silicon in the N− drift layer might suffer localized instances of avalanche breakdown. When avalanche breakdown occurs, electron/hole pairs are produced. Due to the reverse voltage across the device, the electrons flow downward toward the collector, and the holes flow in the opposite direction upward toward the emitter. If avalanche breakdown occurs around the gate oxide, the gate oxide can be damaged. As is known in the art, the junctions between the more heavily doped P+ portions of the P body region and the N− drift layer are therefore fashioned with a convex curvature to have a lower localized avalanche breakdown voltage. If avalanche breakdown were to occur, it would then occur close to these locations and not close to the fragile gate oxide. Reference numeral 10 in FIG. 1B identifies this PN junction. This PN junction is designed to withstand the high currents associated with an avalanche breakdown episode. The deeper P+ type body region 3B1 with its convex curvature is therefore deliberately placed a substantial distance away from the relatively fragile gate oxides so that avalanche breakdown and its adverse effects will be kept away from the gate oxide. In the diagram of FIG. 1B, the avalanche breakdown junction 10 is laterally spaced and separated both from the gate oxide layer of gate electrode 1 to the left, as well as from the gate oxide layer of the gate electrode 11 to the right.
The trench IGBT structure of FIGS. 1A, 1B and 1C sees widespread use and is considered to work well.